This video provides a detailed tutorial on recognizing and reverse-engineering standard cell CMOS logic at the physical layout level, using micrographs of a PIC12F683 microcontroller. The analysis begins with the fundamental CMOS inverter, explaining its transition from a schematic to a physical layout, highlighting the critical design choice of making P-FETs physically larger than N-FETs to achieve balanced drive strengths. This principle is then applied to identify inverter cells on the actual die. The process is extended to a more complex two-input NAND gate, deconstructing its series N-FET and parallel P-FET structure. A significant portion of the video is dedicated to analyzing non-logic "filler cells," revealing them to be decoupling capacitors constructed from MOS gate structures and interdigitated metal fingers. The purpose of these cells is explained as both stabilizing the internal power supply and physically occupying empty space within the logic array to maintain the continuity of power and ground rails.
From Schematics to Silicon: A Guide to CMOS Logic Layout
0:00:02 CMOS Layout Fundamentals: The video aims to explain the physical layout of planar CMOS logic, moving from abstract schematics to the actual microscopic structures found on a silicon chip like the PIC12F683.
0:00:28 The Basic Inverter: A standard CMOS inverter consists of a P-FET connected to the power rail and an N-FET connected to ground. An input signal turns one transistor on and the other off, inverting the logic level at the output.
0:05:50 Key Takeaway: Identifying Transistors by Size: In typical CMOS processes, P-FETs have lower charge carrier mobility than N-FETs. To compensate and create symmetrical switching speeds, P-FETs are designed with a physically wider channel. This size difference (larger P-FET, smaller N-FET) is a crucial visual clue for reverse-engineering the logic.
0:07:05 Identifying an Inverter on the Die: Using micrographs, the video demonstrates how to identify a real-world inverter cell by locating its larger P-FET and smaller N-FET, a shared polysilicon gate, and its connections to power, ground, input, and output.
0:10:54 Deconstructing a NAND Gate: A more complex cell is analyzed and identified as a two-input NAND gate. Its physical structure consists of two N-FETs connected in series for the pull-down network and two P-FETs connected in parallel for the pull-up network.
0:12:54 Uncovering Non-Logic "Filler" Cells: The video investigates unusual-looking cells scattered across the chip that don't function as standard logic gates.
0:15:09 Purpose of Filler Cells: Decoupling Capacitors: These cells are identified as on-die decoupling capacitors. They utilize the parasitic capacitance of MOS gate structures (polysilicon over substrate) and interdigitated metal fingers to stabilize the internal power rails (VDD and Ground) against voltage droops during high-speed switching. They are also used as "filler" to occupy empty spaces in the logic array, which allows for continuous power and ground rails.