This video provides a deep dive into the on-chip SRAM (Static Random-Access Memory) of the PIC12F683 microcontroller. It begins by explaining the fundamental architecture of a standard 6-transistor (6T) SRAM cell, detailing its construction from cross-coupled inverters and the function of word lines and bit lines for read and write operations. The analysis then shifts to the physical implementation on the chip, revealing how the logical 128x8 byte array is physically laid out as a more practical 32x32 bit grid, requiring column multiplexing. The video highlights advanced design techniques, such as parallel metal word lines used to overcome the high resistance of polysilicon. The core of the analysis is the reverse engineering of the row address decoding logic, which initially presents a puzzle: 12 address lines are present for what should be a 5-bit row address. The mystery is solved by consulting the microcontroller's datasheet, which reveals a non-contiguous, banked memory map. The SRAM is split across two separate banks, and the complex decoding logic, including the "extra" address lines, is designed to correctly map the physical rows to this fragmented logical address space.
Reverse Engineering the PI2F683 Microcontroller's SRAM
00:00:07 - The Core of SRAM: The 6T Cell: The fundamental storage element in SRAM is a 6-transistor (6T) cell. It consists of two cross-coupled CMOS inverters forming a stable loop that holds a single bit (a 1 or a 0). Two additional access transistors, controlled by a "word line," connect this storage loop to a pair of "bit lines" to enable reading and writing.
Read Operation: The word line is activated, connecting the cell to the bit lines. A sensitive differential amplifier detects the slight voltage difference on the bit lines to determine the stored value without disturbing it.
Write Operation: The word line is activated, and the bit lines are strongly driven to the desired new state (one high, one low). This powerful external signal overpowers the inverters in the cell, flipping its state to the new value.
00:03:10 - Logical vs. Physical Array Structure: While the PIC12F683 logically provides 128 bytes of RAM (a 128x8 array), it is physically implemented as a 32-row by 32-column grid for layout efficiency. This requires a 4-to-1 column multiplexer to select the correct 8 bits for the data bus from the 32 available in each activated row.
00:04:56 - Moore's Law in Action: A comparison shows the dramatic evolution of semiconductor technology. The SRAM bit cell on the PIC12F683 is 47.15 square microns, while a modern STM32 microcontroller (on a 90nm process) has a bit cell of about 1 square micron. You could fit 47 modern cells in the space of one older cell.
00:06:21 - Overcoming Resistance with Parallel Word Lines: Polysilicon, used for the word lines, has significant electrical resistance, which can slow down memory access. To combat this, a low-resistance metal line is run parallel to each word line, with contacts connecting them every 8 cells. This ensures the activation signal travels quickly across the entire row.
00:15:00 - The Address Decoding Mystery: Reverse engineering the row decoder revealed a puzzle. Since there are 32 physical rows, a 5-bit address is needed (2^5 = 32), which would require 10 differential signal lines (5 pairs). However, the layout clearly shows 12 lines (6 pairs), and the connection pattern is not a simple binary count.
01:16:47 - Key Takeaway: The Banked Memory Map: The solution was found in the datasheet. The 128 bytes of RAM are not in a single, continuous block of memory. Instead, they are split into a 96-byte region in "Bank 0" and a 32-byte region in "Bank 1." The seemingly complex addressing logic and the sixth pair of address lines are necessary to handle this non-contiguous, banked memory architecture, correctly mapping physical rows to their logical address across the two banks.