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GPU Mode: int8 Tensor Core Matmuls for Turing

• 0:00:21 Introduction to the speaker Eric and talk topic: educational, int8 tensor core matmuls for Turing. Goal is to understand the basics rather than achieve state-of-the-art speed.
• 0:01:36 Key point: Int8 matrix multiplication is interesting across various hardware, not just GPUs.
• 0:02:04 Integer multiplication results in a larger data type (8-bit * 8-bit = 16-bit), creating register size mismatches compared to floating-point.
• 0:02:35 AVX-512's VNNI extension and CUDA's dp4a provide instructions for four-way dot products between signed/unsigned integers.
• 0:03:30 Integer math is deterministic, simplifying testing and eliminating the need for tolerance ranges.
• 0:04:39 Demonstrates the use of Tensor Cores directly in CUDA, without relying on large header libraries (e.g., Cutlass) or inline assembly (for functions shown in the video)
• 0:05:04 Question about when inline assembly is required; newer tensor instructions don't have equivalents in C++, war group MMA is a good example of it needing inline assembly. Code for Turing and Ampere is dispatched to correct ISA.
• 0:06:25 If you don't want to go too deep, use Cutlass. If you want to write it on your own, inline assembly is a good choice.
• 0:07:17 Code focuses on nice matrices: large, square, with dimensions divisible by a large power of two.
• 0:08:15 Optimizing for Turing (Quadro RTX 400) because it has fewer features, simplifying the process. There's an online submission system for trying the exercise.
• 0:10:00 Question: What efforts are there to optimize a kernel for a specific GPU, what to pay attention to when hyperspecializing code for it.
• 0:10:32 Difference is between GPU generations. Compiler tries to hide specialities by reordering, and some level of fine tuning is still needed
• 0:10:50 C++ code works for both Turing and Ampere.
• 0:11:53 Specializing for specific GPUs means understanding problem size vs GPU streaming multiprocessors. Tail effects must be considered, select block size to optimize for
• 0:13:06 Emphasis on providing structured feedback to fix errors instead of simple correctness checks. Using structured matrices (e.g., blocks of constant numbers) can help debug.
• 0:14:14 Considers small and large Matrix multiplication. Checks against reference result with naive check.
• 0:15:20 FS algorithm checks product with A and B * Vector X. Also compares qas library, while maintaining focus on code complexity.
• 0:17:43 Define result type with a result fragment (inner product). The speaker re-frames matmul in terms of "fragments", in order to bridge the gap between scalar math and tensor core math.
• 0:18:37 Basic decomposition of the matrix.
• 0:19:19 Question about best precision for certain devices
• 0:20:52 Decompose into fixed size submatrices (divisible by 16). This simplifies the problem, where matrix multiplication at the level of these blocks can be optimized.
• 0:22:21 Cutlass comes with megabytes of header files so just the CUFace is used.
• 0:22:39 Functions used for cuda: Two load, one store, fill and the MMA sync is exactly this multiplying of two matrix fragments.
• 0:22:55 Main Cost is not writing assembler. Code is not optimized for all gpus.
• 0:23:41 Revisits scalar matrix multiplication algorithm in a way that makes parallels to Tensor Cores.
• 0:24:32 Simplest Tensor Core Matrix. Algorithm level hasn't changed as we're defining a 16x16 fragment. Looping in steps of 16 and addressing needs to take into account the thread and block index. Sums come from MMA Sync Instruction. Result is Matrix SYNC and a caveat is provided about the example.
• 0:25:46 After this, are we fast?
• 0:25:49 If running in test mode you see a 4000 gigaflopps!
• 0:26:08 You need to do a speed of light analysis.
• 0:26:35 It isn't that simple to get decent performance even using tensor cores. Need to know the underlying reason for the performance result.
• 0:26:45 Need data in the right places at the right time. Bad memory access pattern! Strided access!
• 0:27:30 The Matrix sync functions fetches data from global memory and distributes it across threads in warp in an unspecified manner. This results in registers of Cuda.
• 0:28:17 The data is strided because B declared to be R major and we get unless Reads and uness Reads are very much terrible.
• 0:28:21 What are we transferring a lot of data from??
• 0:29:00 See 630 gbs of data.
• 0:29:10 Warp stall Cycles
• 0:29:20 Explains what WP stall Cycles are, they explain how many different Cycles that you spend in some state where it didn't do anything useful
• 0:30:07 Bad performance due to war can't hide the memory latencies
• 0:31:12 Specialization of Q C++ over assembly, tested on both ampere and during.
• 0:31:15 One strategy to do you reuse for memory, a large power of the two will result in boundaries problems and you run into boundary issues
• 0:31:45 For the same reason Matrix computations and matrix products are n cubed so it's sufficiently larger. That means a transpose will be cheaper.
• 0:32:29 Don't have to worry about overhead.
• 0:32:41 improved memory because number of requests is down from 60%. A slight drop was seen from L2 cache.
• 0:33:30 Discussion: what to expect with WPS and the data that is written down. There are reasons we are no longer having those big memory
• 0:34:16 Kernel got faster by a good metric 45 percent
• 0:34:35 All the statistics that you need for that are normalized.
• 0:34:50 This is the normal optimizations. Look at the memory and put stuff in the right place.
• 0:35:19 There are different versions of memory, this means registers is the fastest place to put data
• 0:37:18 Goal was to move as much memory access as possible to faster memory to reuse fastest memory that we have
• 0:37:25 A register is a simple step to accomplish. And it is also quite similar
• 0:37:31 Make sure we're using this memory in the right place
• 0:38:21 All of these address locations for the correct information
• 0:38:40 Everything loaded by the right information
• 0:38:51 This comes back full cycle to the pmmp book.
• 0:40:41 If it is not a register we need to use shared memory
• 0:41:25 Now we get back with these registers but on the right track
• 0:41:31 Register spillover
• 0:41:46 Have we ever had a different issue that is important to the data
• 0:42:11 Can do more testing
• 0:43:54 Not end of how you can reuse so
• 0:44:39 To remember graph
• 0:45:01 The discussion of having some more feedback
• 0:45:16 Main point is to reuse
• 0:45:43 If not share memory could help out
• 0:46:45 See more share memory we did a copy to the share memory is vectoring now
• 0:47:31 Want to talk data and we show you the details
• 0:47:55 There is alignment as the data and that helps make memory transfers and you transfer to the share memory
• 0:49:18 Data is correct in some way
• 0:49:58 So the goal was to prevent you from using any core power, and to have to to read it directly from the hardware
• 0:50:17 This process helps provide you the the trade-off from many futures! and does not make asynchorn
• 0:50:31 Now with the copy with load sync and store there
• 0:50:58 Then you loop it is really helpful
• 0:51:20 Get the data and see different stuff going on that is helpful
• 0:51:55 See 80% different
• 0:52:17 Does some one see a problem that it might cause
• 0:53:08 Guess spill in the right direction
• 0:54:20 So, the reason why we didn't have a core data and didn't had a small problem as we did at before is because we force them to use specific numbers by design and code the way that we do
• 0:54:46 Does the trade offs make sense so what we can say is we might see problems in that particular core
• 0:55:13 If we go for long scoreboard it tells about how the data that's being used and where it's going
• 0:56:05 If we run the benchmark we can see these details
• 0:56:50 This data is really simple
• 0:58:44 Try to provide the details
• 0:59:56 Discussion to the audience with an expert
• 1:01:09 Going to talk about pmpp techniques
• 1:01:34 The thing has to load, what is it, the data?
• 1:01:50 Is it really useful if someone can give an idea
• 1:03:36 There is different amount of data that is on the site
• 1:04:07 That is being given
• 1:05:31 What does the next steps look like?
• 1:05:40 The thing is going to change! How about the different steps that needs to be taking?
• 1:11:55 So is there a reason for this?
• 1:12:51 Also need you to understand the information as well
• 1:13:18 We know a way to do a lot of math
• 1:14:00 Does the information provide what that means
• 1:14:40 The details can be mentioned so
• 1:15:47 If people need more information Eric is in the chat.
• 1:16:25 If you're interested let me know
• 1:16:38 Closing summary.