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INT8 Tensor Core Matmuls for Touring GPUs
0:00:21 Introduction: Eric Schulte discusses int8 tensor core matmuls on Touring GPUs, emphasizing the educational goal of the presentation.
0:00:36 Why int8?: Eric explains the benefits of using int8 matrix multiplication due to their determinism compared to floating-point operations.
0:00:55 Importance of Good Questions: The presenter, Eric, encourages interactive questions about the content.
0:00:57 Presentation Goal and Scope: The main goal is to demonstrate basic tensor core usage directly in CUDA without external libraries or inline assembly.
0:02:55 CUDA Four-Way Dot Product: There is a four-way dot product instruction that takes 4 8-bit integers that accumulates into a single 32-bit accumulator.
0:03:31 Tensor Cores for Turing: Eric highlights that Tensor Cores work from Turing onwards.
0:05:04 Inline Assembly: Newer tensor instructions lack C++ equivalents.
0:05:18 Inherent Lag: The kinds of things being represented are not representable with very simple C++ code.
0:07:07 Code Specifics: The code being discussed is optimized for large, square matrices that are divisible by a large power of two for simplicity.
0:08:12 Turing Optimization: The tutorial is optimized specifically for Touring due to simpler features and availability on a submission system.
0:08:57 Online Submission System: An online system is available for users to try out the described techniques and test their code.
0:09:59 Optimizing Kernels A question is raised about efforts to optimize a kernel for a specific GPU.
0:10:35 GPU Generation Differences: Different generations of GPUs have different types of tensor instructions with differing computability.
0:12:17 Tail Effect: Discussing the tail effect, where some streaming multiprocessors take longer to run than others.
0:13:15 Testing and Debugging Challenges: Random Matrix testing isn't useful for debugging but structured matrices help find block boundary errors.
0:13:53 Useful Testing Approach: Structured matrix operations are beneficial for finding bugs.
0:15:20 Special Matrix Properties for Testing: The presentation proposes using special matrices like identity matrices for testing the correctness of algorithms.
0:15:38 Computational Perspective for Testing: The FS Algorithm is a useable property to test the efficiency of matrix computation.
0:15:50 Algorithm Performance Comparison: Naive algorithm vs KNIVE Matrix vs Faster algorithms.
0:17:43 Demonstration Goal: Demonstrate the basic use of Tensor Cores in CUDA, avoiding assembly or external libraries.
0:17:50 Naive Scalar Matrix Multiplication: The presenter starts by revisiting the naive scalar matrix multiplication algorithm.
0:20:00 Accumulation Hardware: The accumulation into in32 happens inside the tensor core.
0:20:04 Problem of the stress algorithm: Gives lots more matrix additions which, in O notation, are cheap. In real-world usage, this is false.
0:20:15 Fixed Matrix: Decomposing it into submatrices of a fixed size can be helpful.
0:21:17 Optimizing Data: Discussing typical problems that one has when trying to get anything fast on GPUs.
0:21:33 Submatrix Fragmentation: Naive algorithm is easier when matrices are decomposed into a block size.
0:22:21 QFace A limited amount of functions are needed for this.
0:23:15 Matrix Fragment Mapping: The mapping of Matrix elements into fragments is unspecified and subjective.
0:24:25 Naive vs Simplest Tensor Core Matrix multiplication There is no real change in alg level, just definition of 16x16 fragment types.
0:24:34 Tensor Core Performance: The example runs at 4,000 gigaflops but that's orders of magnitude away from supposed to get.
0:25:51 Performance Issues: Speed-of-light analysis needed due to high FLOPS, suggesting significant inefficiencies. Speed of light would be using 100% of tensor cores.
0:26:44 Improving Performance: Data Placement: Key to making GPU computing work is ensuring data is in the right places at the right time.
0:27:16 Memory Access Pattern Issues: Load Matrix sync fetches data from Global memory and distributes it across threads.
0:28:00 Bad Matrix B: Uncorrelated Reads are terrible for performance and the accesses are strided.
0:28:15 Graph of What To Improve: Transfer from A2 cache and L1 cache is what should improve.
0:29:17 Warp Stall Cycles: Explanation of warp stall cycles metric in Nsight Compute (ncu). Top contenders are throttle AGG and stall long scoreboard.
0:30:20 High Warp Stall Cycles: This results in warps running for longer and most being idle.
0:31:05 Fixing with Column Major Matrix B: Column major format is the solution with the definition of the W fragment and indexing in Load Matrix synch.
0:31:13 High Memory Bounds: In the grand scheme of things, this improves Big O notation, because one will want transpose.
0:32:00 Memory Read DecreaseThe requests decrease by 60%.
0:33:30 Initial Problem Results: Not getting shorter stalls because a graph from Compute.
0:33:59 Instructions ReduceBecause now we're using far more load instruction.
0:34:20 Improving More Using standard Cool optimization kit.
0:34:35 Key Goal: Reuse memory in registers and the only way to do that is by each thread handling more of the output result.
0:34:40 The graph on this powerpoint Has the same thing, but the graph is slightly different in that it is a pyramid. The interesting stuff is happening at the top of the pyramid
0:34:55 How to Implement: At beginning of loop, you would load the three um results.
0:34:14 DrawbacksThe question is whether this has any.
0:41:50 Register Need Depends on Whether your inputs or 32-bit FLOPS or integers.
0:42:10 Main Message: What you're doing is the same recipe as a scaler matrix multiplication.
0:42:40 Increased Occupancy The reason its not faster is occupancy.
0:42:54 Register Spilling vsThe key here to not over-reuse those.
0:42:50 Question: How come started with 3 fragments? There could be 2, but that is part of why the development exists to create those.
0:44:59 There's one more in the SM and has not been used, Shared Memory
0:46:50 Discussion about what is needed to do what, what you want that does not involve Q scores?
0:46:55 Reuse that in Share memory to make faster, but it needs quotations since that is something to implement and not inherently an asset.
0:46:54 How this goes down? If there is more time at the end of the presentation, there are other things can do, like more asynchronous instructions.
0:47:57 What is not being done for the 3x3 tile setup
0:52:30 The question, and answer, for the reasons, for the number with a crazy percentage and the answer to the problem.
0:52:43 There are various options to take.
0:53:00 Inforce, force that is info to the GPU.
0:53:41 Why can you use more memory?
0:53:50 There were many more improvements, so this is to give more information.
0:53:34 L and O To use Global L, need a 16-bit boundary; memory load need that to help it work.
0:54:54 To know about the terms, you can use Perplexity or Google.
0:55:30 How would this impact this?
0:57:15 the goal is to have standard PPB but we want other things to get a lot of code because they need a lot of functions.
1:01:11 The big idea, if not getting, there, to just do to do this memory, registers to thread indies.
1:01:33 There is what may not be obvious the high level that comes to mind, and all the issues of shared memory.
1:04:06 V is not a big one.
1:04:34 Memory and scoreboard is a huge one.
**1:06:28 If did have more than a block, there is not as many.
1:07:10 Why the changes in the 80's
**1:07:50 How to get the results.
1:08:10 I see all what. I'll keep in mind
1:08:21 What might have that caused: There were very few L Global.
**1:08:30 It to mention in.
1:08:50 Instructions, not be generating.
1:11:48 To load early, to save on many Global stall, not for sure on what this effect does, so, Eric is very uncertain in this.
1:12:26 Then he runs a speed-to- light thing, just not what to do.
1:13:21 That will continue later on:
1:13:51 The rest for and at the end.
1:14:48 Thank you, great job, excellent.
1:15:15 A big thanks
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